Exemplary embodiments relate to a method of manufacturing a semiconductor device.
In the related art, in electronic devices such as semiconductor devices, the utilization of multi-layer interconnections is used in order to achieve high integration. With respect to a semiconductor device having multi-layer interconnections, when electrically connecting upper and lower wiring patterns that are disposed with an interlayer insulator layer therebetween, contact holes are formed in the interlayer insulator layer. Through the contact holes, the upper and lower wiring patterns are connected.
In the related art, in a method of making a multi-layer interconnection, a film of a conductive material such as metal and polycrystalline silicon is formed on a substrate. By etching the film, a lower wiring layer is formed. Next, while an interlayer insulator layer is formed on the lower wiring layer, predetermined openings (contact holes) are formed in the interlayer insulator layer using a photolithography method. Further, a conductive material as a contact plug is applied onto the whole area of the interlayer insulator layer in a manner to fill the formed contact holes, and then patterning is performed by a photolithography method, thus a contact plug is made. Then, a film of a conductive material for wiring on the upper layer is formed in a manner to connect with the contact plug. Patterning this film by a photolithography method forms an upper wiring layer (for example, International Patent Publication No. WO 00/59040).